The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in test, validation, yield, reliability, and security of microelectronic circuits and systems.
The symposium will take place on April 28-30 2025, in Tempe, AZ, USA.

The program includes keynotes, scientific paper presentations, short industrial application paper presentations, special sessions, and Innovative Practices sessions.

You are invited to participate and submit your contributions to VTS’25. The areas of interest include (but are not limited to) the following topics:

VTS Topics

    Generative AI Applications in Test and Security
    Silicon Lifecycle Management
    Silent Data Corruption
    Test-Enabled Digital Twin
    Analog – Mixed-Signal – RF Test
    ATPG & Compression
    Automotive Test & Safety
    Built-In Self-Test (BIST)
    Functional safety
    Digital twin enabled test and security
    High BW Test through High-Speed Interfaces
    Testing for extreme environments
    Test og Non-Si & Compound Circuits
    Test and Security of Quantum Circuits
    Test and Security of Photonic Circuits
    Test and Security of Emerging Memory Technologies
    Functional Debug through Scan
    Fault Modeling and Simulation
    Low-Power IC Test
    Machine Learning for Test & Security
    Microsystems/MEMS/Sensors Test
    Memory Test and Repair
    Test for 3D & Heterogenous Integration
    Yield Optimization
    On-Line Test & Error Correction
    Power & Thermal Issues in Test
    System-on-Chip (SOC) Test
    Test & Reliability of Biomedical Devices
    Test & Reliability of High-Speed I/O
    Test & Security of Machine Learning Hardware
    Test Standards
    FPGA Test
    Defect-Based Test
    Defect & Fault Tolerance
    Delay & Performance Test
    Design for Testability
    Post-silicon Validation & Debug
    Hardware Security
    Embedded System & Board Test