Embedded Hardware Design
Affiliated with Euromicro

Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC).

Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.

Special Issue on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
Submission Date: 2024-11-30

Defect and fault tolerance in VLSI and nanotechnology systems including emerging technologies, RISC-V architectures and AI-based solutions, are pervasive topics spanning domains and applications. This special issue features both new academic research and state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, availability, and security that are affected by defects during manufacturing and by faults during system operation are of interest.

Guest editors:

Dr. Jaume Abella

Computer Architecture and Operating Systems Interface (CAOS) Group Leader Barcelona Supercomputing Center (BSC), Barcelona, Spain

Email: jaume.abella@bsc.es

https://www.bsc.es/discover-bsc/organisation/scientific-structure/computer-architecture-operating-systems-caos

Jaume Abella co-leads the CAOS research group (embedded systems group) at BSC, where he works since 2009. Before, Jaume got his PhD (2005) and worked as Senior Researcher at Intel Corporation (2005-2009). Jaume leads the Horizon Europe SAFEXPLAIN project, and is (has been) the PI at BSC of several EU projects on enabling the use of high-performance hardware and software, as well as AI in safety-critical systems, in different funding frameworks such as Horizon Europe (NimbleAI, SAFEXPLAIN), Chips JU (SMARTY, ISOLDE, REBECCA), H2020 (SELENE, DeRISC, SAFURE), ECSEL (FRACTAL) and ARTEMIS (VeTeSS). Jaume has chaired the OpenHW Group Safety&Security Task Group (2023-2024) and vice-chaired the RISC-V International SIG-Safety (2022-2024). Dr. Abella holds 15 patents issued, has published around 250 papers in top peer- reviewed conferences and journals, has co-advised 15 PhDs and 20 Master theses, and co-founded a successful spinoff providing software services in avionics and automotive (Maspatechnologies S.L., now Rapita Systems S.L.). Jaume has been awarded with the most renowned national (Ramon y Cajal) and regional (Beatriu de Pinós) personal grants in Spain and Catalonia respectively. Jaume has organized a number of workshops, and tutorials, and given invited talks in topics related to functional safety and real-time systems in a number of venues (e.g., the opening keynote at the 28th Ada-Europe International Conference on Reliable Software Technologies, 2024). Jaume has been TPC member in around 50 conferences and workshops in the area of dependability and computer architecture including DATE, DFT, ETS, ICCD, and IOLTS among others, has been topic chair (3 times) and track chair (once) in DATE, and is the TPC co-chair of DFT’24. Jaume is also associated editor of the IEEE Transactions on Computers since 2022, and teaches functional safety for automotive systems at a Master program of the Universitat Politecnica de Catalunya (Spain) since 2018.

Dr. Adrian Evans

Research Engineer CEA/LIST, Grenoble France

Email: adrian.evans@cea.fr

Adrian Evans is a Research Engineer at CEA/LIST where his work focuses on fault tolerance and energy efficient compute solutions. Previously, he worked as a Senior Technical Leader at Cisco Systems (1999-2011) and as a Principal Engineer at IROC Technologies (2012-2017). He is the author or co-author of approximately 45 publications in international conferences or journals and is inventor / co-inventor of 6 patents. He has served on the TPC of several international conferences (DATE, IOLTS, DFTS, IRPS) and regularly reviews papers for journals such as IEEE TDMR and IEEE TNS. Adrian has co-organized several workshops at international conferences such as the recent CITaR workhop at ETS 2024 and he is an active member of the IEEE P3405 committee on repair of chiplet interconnects. He has given invited talks at international companies, such as at Huawei’s Engineering Innovation Days and presented invited talk/papers at conferences such as IRPS, ETS and DATE.

Special issue information:

Defect and fault tolerance in VLSI and nanotechnology systems including emerging technologies, RISC-V architectures and AI-based solutions, are pervasive topics spanning domains and applications. This special issue features both new academic research and state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, availability, and security that are affected by defects during manufacturing and by faults during system operation are of interest. Topics include (but are not limited to) the following:

1. Yield Analysis and Modeling

Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.

2. Testing Techniques

Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity.

3. Design For Testability in IC Design

FPGA, SoC, NoC, ASIC, low power design and micro-processors, including RISC-V architectures

4. Error Detection, Correction, and Recovery

Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural and system-level techniques.

5. Dependability Analysis and Validation

Fault injection techniques and frameworks; dependability and characterization, cross-layer reliability analysis, dependability analysis for AI and machine learning.

6. Repair, Restructuring and Reconfiguration

Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems.

7. Defect and Fault Tolerance

Reliable circuit/system synthesis; fault tolerant processes and design; design space exploration for dependable systems, transient/soft faults.

8. Radiation effects

SEEs on nanotechnologies; modeling of radiation environments; radiation experiments; radiation hardening techniques.

9. Aging and Lifetime Reliability

Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery.

10. Dependable Applications and Case Studies

Methodologies and case studies: 2.5D/3D ICs, IoT, automotive/railway/avionics/space, autonomous systems, industrial control, fail-safe systems, dependable AI.

11. Emerging Technologies

Error management techniques for quantum computing, memristors, spintronics, microfluidics, approximate computing, etc.

12. Design for Security

Fault attacks, fault tolerancebased countermeasures, scan-based attacks and countermeasures, hardware trojans, system obfuscation and logic locking, secure AI, security vs. reliability, interaction between VLSI test, trust, and reliability.

Extended journal versions of invited papers from the 37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems 2024 are welcome. Extended papers must contain at least 30% of new material different from the original work published in the conference proceedings possibly with a reformulated text of the unmodified parts.

Manuscript submission information:

Important Dates:

    Submission Deadline: 30 November 2024
    First Round Decisions: 28 February 2025
    Revised Papers Submission: 15 April 2025 
    Decisions for the Revisions: 31 May 2025 
    Camera Ready Deadline: 30 June 2025

All manuscripts should be submitted via the Elsevier online system of the journal, available at https://www.editorialmanager.com/MICPRO. When submitting the paper, please select “VSI: DFTS 2024” as the article type.